Field of the Invention
The invention relates, in general, to an integrated memory and, in particular, to a memory cell array with a configuration of supply lines having a low resistance.
Integrated memories, such as DRAMs (Dynamic Random Access Memories), generally have a multiplicity of memory cells which are configured at crossing points or adjacent regions of overlap of word lines and bit lines. The word lines are each configured parallel to one another and are at regular distances from one another. The bit lines are each configured parallel to one another and are at regular distances from one another. The configuration of memory cells along the word lines and bit lines is called a memory cell array. It is often necessary to supply particular potentials and signals to regions within the cell array. These potentials can be supplied by lines running outside the cell array and parallel to one of the edges of the cell array. These lines branch off toward the inside of the cell array where they are connected to the regions that are to be supplied with the respective potential. This produces the following problem: as the extent of the cell array increases (its extent increases with higher storage capacities), the relatively poorly conductive branch lines within the cell array increase in length. The branch lines are necessary for conveying the potentials and branch off from the (main) supply lines routed along the cell array. The result of the increasing line lengths is an increased line resistance, which makes the potentials that are to be supplied susceptible to faults caused by fluctuations in the supply potential, for example.
It would therefore be desirable to route the main supply lines necessary for supplying the potentials to the regions that are to be supplied not only at the periphery of the cell array but also in the center of the cell array. This would either eliminate the poorly conductive branch lines described or would keep them as short as possible. A conflicting consideration, however, is the fact that the structures forming the bit lines and word lines and the structures forming the memory cells that are configured at the crossing points of the word and bit lines should be configured as regularly as possible in order to achieve the best production process. In addition, producing memory cell arrays which are as compact as possible requires minimizing the distances between the word lines and the distances between the bit lines. Therefore, it is not possible, without using further wiring planes, to route the supply lines in the center of the memory cell array without interrupting the regular structure of the word and bit lines at these points.